Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

A method for processing a semiconductor structure and a method for forming a word line structure are provided. The method for processing the semiconductor structure includes: providing a semiconductor structure including a groove and a metal layer located in the groove, where an edge position of a top surface of the metal layer is higher than a center position of the top surface of the metal layer; enabling the semiconductor structure to be in a rotating state; and performing at least one metal surface planarization process on the semiconductor structure, so that the top surface of the metal layer after being processed is more planar than the top surface of the metal layer before being processed. Each of the at least one metal surface planarization process includes: etching the top surface of the metal layer by a first reagent; and cleaning the semiconductor structure by a second reagent.

A semiconductor structure includes: a base; a first conductive layer, having a portion located within the base and a remaining portion protruding above the base; a barrier layer on the base and at least on a sidewall of the first conductive layer protruding from the base; a dielectric layer on the barrier layer; and a second conductive layer penetrating the dielectric layer and the barrier layer, in contact with the sidewall of the barrier layer, and in contact with at least a portion of the upper surface of the first conductive layer.

The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

A method of forming a cap layer for sealing an air gap is provided. The method includes forming a line feature over a substrate, forming a contact etch stop layer (CESL) on a sidewall of the line feature, forming a sacrificial layer on a sidewall of the CESL, forming a liner layer on a sidewall of the sacrificial layer, removing the sacrificial layer to form an air gap which is bordered at the CESL and the liner layer and which is adjacent to the line feature, etching back upper ends of the CESL and the liner layer to widen an opening of the air gap, and forming a cap layer to seal the opening of the air gap thus widened.

Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.