A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer.

A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.

A method of manufacturing a semiconductor structure includes: forming a first opening in a first dielectric material; forming a first barrier layer in the first opening; forming a first seed material including copper and manganese on the first barrier layer, in which the manganese in the first seed material is in a range of from 0.10 at % to 0.40 at %; forming a first conductive material on the first seed material; and moving at least some of the manganese of the first seed material to a location proximate an interface between the first seed material and the first barrier layer. Another method of manufacturing a semiconductor structure and a semiconductor structure are also provided.

A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer.

A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.