Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

Embodiments of the present technology relate to semiconductor processing methods that include providing a structured semiconductor substrate including a trench having a bottom surface and top surfaces. The methods further include depositing a portion of a silicon-containing material on the bottom surface of the trench for at least one deposition cycle, where each deposition cycle includes: depositing the portion of the silicon-containing material on the bottom surface and top surfaces of the trench, depositing a carbon-containing mask layer on the silicon-containing material on the bottom surface of the trench, where the carbon-containing mask layer is not formed on the top surfaces of the trench, removing the portion of the silicon-containing material from the top surfaces of the trench, and removing the carbon-containing mask layer from the silicon-containing material on the bottom surface of the trench, where the as-deposited silicon-containing material remains on the bottom surface of the trench.

A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb.sub.2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb.sub.2N sacrificial layer; growing a Ta.sub.2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta.sub.2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb.sub.2N sacrificial layer and the Ta.sub.2N sacrificial layer; and transferring remaining material after removal of the Nb.sub.2N sacrificial layer and the Ta.sub.2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

In a method according to an exemplary embodiment, a substrate is prepared in a chamber. A patterned resist mask has been formed on a first region of the substrate. A surface of the substrate in a second region is exposed. A film is formed on the substrate in the chamber by sputtering. The film is formed on the substrate in a manner that particles emitted obliquely downward from a target are caused to be incident onto the substrate.

A trench field-effect transistor (FET) device includes a plurality of active trenches extending along a first axis and distributed along a second axis perpendicular to the first axis. Each active trench includes a gate electrode and a shield electrode. The trench FET device further includes a plurality of termination trenches fully filled with a dielectric material, extending along the second axis, and arranged adjacent to the active trenches. In addition, the shield electrode of each of the active trenches abuts a respective one of the plurality of termination trenches at each end.

The present application discloses a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a conductive line of an N.sup.th metal layer, a first insulating layer, a dielectric layer, a second insulating layer, an interconnect base, and an interconnect body. The first insulating layer is on the conductive line and free from covering a portion of the conductive line. The dielectric layer is on the first insulating layer and free from covering the portion of the conductive line. The second insulating layer is on the dielectric layer and free from covering the portion of the conductive line. The interconnect base is laterally surrounded by the dielectric layer, the first insulating layer, and the second insulating layer. A top surface of the interconnect base and a top surface of the second insulating layer are coplanar.

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

An Inorganic Lift-Off-Profile-Process (referred to herein as ILOPP) is described wherein a portion of a surface inorganic oxide is etched from a substrate oxide surface and under a photoresist edge that supports a sacrificial metal layer. This oxide etched profile under the sacrificial photoresist/metal edge improves Lift-Off of the sacrificial metal layer and delivers smoother, improved metal edge definition in addition to an improved planer surface (flatness) as compared to known LOP technologies.