Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate.

An electronic structure and a method for fabricating the same are provided. An electronic component and conductive elements are disposed on a carrier. An encapsulation layer encapsulates the electronic component and the conductive elements. The encapsulation layer has concave portions corresponding in position to the conductive elements. Each of the conductive elements is in no contact with corresponding one of the concave portions.

Methods for filling a substrate feature with a seamless gap fill are described. Methods comprise forming a metal film a substrate surface, the sidewalls and the bottom surface of a feature, the metal film having a void located within the width of the feature; treating the metal film with a plasma; and annealing the metal film to remove the void.

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

Methods and apparatus for forming an interconnect structure, the method including selectively depositing two or more capping layers atop a top surface of a via within a low-k dielectric layer, wherein the two or more capping layers include a first layer of ruthenium and a second layer of cobalt.

Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

An integrated circuit has a first layer having a recess that extends into the first layer. In addition, a second layer is within the recess and comprises a metal or a dielectric, and a third layer is within the recess and between the first and second layers, the third layer including a material that resonates at microwave frequencies (e.g., 2.4 GHz to 2.5 GHz). In some cases, the third layer material includes: (1) oxygen along with indium and/or zinc; or (2) diethylene glycol dibenzoate. In some cases, such as where the first layer comprises a dielectric (e.g., silicon dioxide) and second layer comprises a metal (e.g., copper), the integrated circuit further includes a fourth layer (e.g., barrier layer including tantalum or titanium) between the second and third layers. The third layer resonates in response to microwave annealing, thereby selectively heating the second layer (e.g., to reflow and/or grow grain size).

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

A magnetically enhanced plasma apparatus includes a hollow cathode target assembly; an anode positioned on top of the hollow cathode target assembly, thereby forming a gap between the anode and the hollow cathode target assembly; a cathode magnet assembly; a row of magnets that generate a magnetic field in the gap and a magnetic field on a surface of the hollow cathode target assembly with the cathode magnet assembly such that magnetic field lines are substantially perpendicular to a surface of the hollow cathode target assembly; an electrode positioned adjacent to the row of magnets behind the gap; a first radio frequency (RF) power supply coupled to the electrode, wherein the electrode is coupled to ground through an inductor; and a second radio frequency (RF) power supply coupled to the hollow cathode target assembly. The second RF power supply ignites and sustains plasma in the hollow cathode target assembly. A frequency and power of the second RF power supply are selected to increase at least one of a degree of dissociation of feed gas molecules and degree of ionization of feed gas atoms. A frequency and power of the first RF power supply are selected to increase a degree of dissociation of feed gas molecules to form a layer from sputtering hollow cathode target material onto a substrate.