Methods of forming a semiconductor device structure are described. The method includes forming a first conductive feature including a conductive fill material over a substrate, forming an etch stop layer on the conductive fill material, forming an intermetallization dielectric on the etch stop layer, forming an opening in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material, forming a recess in the exposed portion of the conductive fill material, and the opening and the recess together form a rivet-shaped space. The method further includes forming a second conductive feature in the rivet-shaped space and forming a metal nitride layer over the intermetallization dielectric and the second conductive feature. The forming the metal nitride layer includes depositing the metal nitride layer and treating the metal nitride layer with a plasma treatment process.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

A method for forming a semiconductor device includes the following: after sacrificial side walls are formed on the side walls of conductive connection structures, forming an outer side wall material layer on the surfaces of the sacrificial side walls; perforating the outer side wall material layer to form pinholes in the outer side wall material layer which expose the surfaces of the sacrificial side walls; removing the sacrificial side walls through the pinholes to form air gaps; and forming a cover layer for sealing the pinholes.

A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H.sub.2) or ammonia (NH.sub.3) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.

A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Methods and systems for cleaning and treating a surface of a substrate. An exemplary method includes providing a substrate comprising a gap comprising a metal oxide and a dielectric material within a reaction chamber, and using a thermal process to selectively remove the metal oxide. Exemplary methods can further include a step of depositing a metal-containing material within the gap to at least partially fill the gap and using a direct plasma and treating a surface of the metal-containing material to remove oxygen from the surface of the metal-containing material. Exemplary systems can perform the methods.

A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer. The structure also includes a second feature formed in a second dielectric layer which has a second barrier layer disposed on vertical surfaces of the second dielectric layer and two vertical surfaces of the copper layer and a bottom surface of the first copper layer is disposed over the first barrier layer.

A device comprises a first dielectric layer, a first conductor, a carbon-containing etch stop layer, a second dielectric layer, and a second conductor. The first conductor has a lower portion in the first dielectric layer. The carbon-containing etch stop layer wraps an upper portion of the first conductor. The second dielectric layer is over the carbon-containing etch stop layer. An interface formed by the second dielectric layer and the carbon-containing etch stop layer is higher over the first conductor than over the first dielectric layer. The second conductor is in the second dielectric layer.