A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.

Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off conditionand a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.

In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.

A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.

Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

Provided is a semiconductor device including a substrate having a first conductivity type, a first well having a second conductivity type, a first doped region having the first conductivity type, a second well having the second conductivity type, at least one second doped region having the first conductivity type, at least one third doped region having the second conductivity type, and a fourth doped region having the second conductivity type. The first well is located in the substrate. The first doped region is located in the first well. The second well is located in the first well. The second doped region is located in the first doped region. The third doped region is located in the first well at a first side of the first doped region. The fourth doped region is located in the first well at a second side of the first doped region.

A semiconductor device that is composed of an epitaxial semiconductor material stacked structure that includes a first epitaxial channel for a first junction field effect transistor (JFET) atop a supporting substrate and a second epitaxial channel region for a second junction field effect transistor (JFET). A commonly electrically contacted source/drain region for each of the first JFET and the second JFET is positioned at an interface of the first and second epitaxial channel region. A channel length for each of the first and second is substantially perpendicular to an upper surface of the supporting substrate. An epitaxial semiconductor gate conductor in direct contact with each of said first epitaxial channel region and the second epitaxial channel region.

In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.

In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side. The first device side comprises a column of a second type in contact with the first column, the substrate, and the first surface of the device; a second column of the first type in contact with the substrate and the second column; a third column of the first type in contact with the substrate and the second column; a first region of the first type disposed in contact with the third column; a second region of the first type disposed in contact with the source and with a third region of the first type; and a first trench comprising the second type and a first region of the second type, wherein the first region of the second type is in contact with a gate region.