A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

A semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. The semiconductor device also includes a gate spacer structure having a first spacer portion and a second spacer portion on opposite sidewalls of the gate structure. The semiconductor device also includes a source region and a drain region formed in the semiconductor substrate. The source region and a drain region are separated from the gate structure. The source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the gate spacer structure. The bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.

A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of .sup.18O greater than 10 percent.

A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of .sup.18O greater than 10 percent.

A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a conductive structure and a gate dielectric layer, and a top of the gate dielectric layer is higher than a top of the conductive structure. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.