Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another. In the context of nanowire based semiconductors, in which NMOS and PMOS nanowires are incorporated as channel, drain and source regions respectively for NMOS and PMOS nanowire transistors, independent tuning of the NMOS and PMOS nanowires facilitates independent tuning of short-channel effects, gate drive, the width of the transistor dead space capacitance, strain and other performance related characteristics of associated NMOS and PMOS nanowire transistors.

Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

A semiconductor device and a manufacturing method thereof are provided. The gate structure and the source and drain terminals are located in the insulating dielectric layer, and the source and drain terminals are located respectively at both opposite ends of the gate structure. The channel region is sandwiched between the gate structure and the source and drain terminals and surrounds the gate structure. The channel region extends between the source and drain terminals.

A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

A semiconductor structure includes a layered dipole structure formed upon a fin sidewall within a fin trench. The layered dipole structure includes a dipole layer of opposite polarity relative to the polarity of the fin and reduces source to drain leakage. A semiconductor structure may include a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.

To provide a novel method for manufacturing a semiconductor device. To provide a method for manufacturing a highly reliable semiconductor device at relatively low temperature. The method includes a first step of forming a first oxide semiconductor film in a deposition chamber and a second step of forming a second oxide semiconductor film over the first oxide semiconductor film in the deposition chamber. Water vapor partial pressure in an atmosphere in the deposition chamber is lower than water vapor partial pressure in atmospheric air. The first oxide semiconductor film and the second oxide semiconductor film are formed such that the first oxide semiconductor film and the second oxide semiconductor film each have crystallinity. The second oxide semiconductor film is formed such that the crystallinity of the second oxide semiconductor film is higher than the crystallinity of the first oxide semiconductor film.

A method for manufacturing a novel semiconductor device is provided. The method includes a first step of forming a first oxide semiconductor film over a substrate, a second step of heating the first oxide semiconductor film, and a third step of forming a second oxide semiconductor film over the first oxide semiconductor film. The first to third steps are performed in an atmosphere in which water vapor partial pressure is lower than water vapor partial pressure in atmospheric air, and the first step, the second step, and the third step are successively performed in this order.

In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.

Provided is a fastening member which is a columnar fastening member, and the fastening member includes: a first hole provided in a direction parallel to a height direction of the fastening member; a thread on a side surface of the first hole; a planar portion around the first hole; and a projection between the planar portion and the first hole.