According to a certain embodiment, the semiconductor device includes: a semiconductor region having a first conductivity type including a first surface; an insulating portion formed on the semiconductor region, and having a second surface moved backward in the depth direction of the semiconductor region more than the first surface; a first region disposed on the semiconductor region between a first portion and second portions of the insulating portion; a second region disposed on the semiconductor region between the first and second portions to be separated from the first region; a control electrode disposed above the first surface to be located between the first and second regions; a first electrode disposed on the first region so as to be contacted with the first region; and a first insulating film containing hafnium disposed on a side wall of the semiconductor region at a stepped portion between the first and second surfaces.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.

A semiconductor device includes an active region through which a main current passes during an ON state. In the active region, the semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, first trenches, a second trench, a polycrystalline silicon layer provided in the second trench via one of the gate insulating films, and a silicide layer selectively provided in a surface layer of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicide layer are electrically connected with the gate electrodes.

A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.

The present application discloses a method for fabricating a semiconductor device includes providing a substrate, forming a gate stack on the substrate and a pair of heavily-doped regions in the substrate, forming a programmable contact having a first width on the gate stack, and forming a first contact having a second width, which is greater than the first width, on one of the pair of heavily-doped regions.

An integrated circuit chip and a method of fabricating the IC chip to include a transistor having a thick gate oxide in combination with STI. The method provides a wafer for which a source region location, a drain contact region location, an extended drain region location and a gate region location have been defined and forms an STI structure overlying the extended drain region location. After growing a gate oxide layer over the gate region location and a portion of the extended drain region location, the method forms a gate structure on the gate oxide layer, the gate structure having a gap overlying the intersection of an edge of the STI structure with the gate oxide layer.

A high voltage semiconductor device includes a semiconductor substrate, a first doped well, a second doped well, a mixed doped well, and a gate structure. The first, the second, and the mixed doped wells are disposed in the semiconductor substrate. At least a part of the first doped well and at least a part of the second doped well are located at two opposites sides of the gate structure in a horizontal direction respectively. The mixed doped well are located between the first doped well and the second doped well. The first and the second doped well include a first conductivity type dopant and a second conductivity type dopant respectively. The mixed doped well includes a mixed dopant. A part of the mixed dopant is identical to the first conductivity type dopant, and another part of the mixed dopant is identical to the second conductivity type dopant.