A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.

A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor strip structure over a semiconductor substrate. The semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, and the spacing region is an undoped region. The method includes performing an implantation process over the first doped region and the spacing region to convert a first upper portion of the first doped region and a second upper portion of the spacing region into a continuous disorder region. The method includes forming a metal-semiconductor compound layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region after the implantation process.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune device performance and enable higher cut-off frequencies without compromising resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A narrow-highly-doped channel may be formed under a narrow gate extension to improve operating frequencies. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.