A semiconductor structure includes a capacitor structure comprising an active region comprising opposing field edges parallel to a first horizontal direction and a gate region comprising opposing gate edges parallel to a second horizontal direction transverse to the first horizontal direction. The semiconductor structure also comprises a first dielectric material adjacent at least one of the opposing field edges or the opposing gate edges and a second dielectric material adjacent the active area and abutting portions of the first dielectric material. A height of the second dielectric material in a vertical direction may be less than the height of the first dielectric material. Semiconductor devices and related methods are also disclosed.

A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

A method includes forming a gate structure over a substrate; forming a first gate spacer and a second gate spacer on opposite sidewalls of the gate structure, respectively; implanting a first dopant of a first conductivity type into the substrate form a lightly doped source region adjacent to the first gate spacer, and a lightly doped drain region adjacent to the second gate spacer; forming a patterned mask over a first portion of the lightly doped drain region, while leaving a second portion of the lightly doped drain region exposed; and with the patterned mask in place, implanting a second dopant of the first conductivity type into the substrate, resulting in converting the second portion of the lightly doped drain region into a drain region.

A semiconductor device is provided. The semiconductor device comprises a substrate having a wide bandgap semiconductor material and an epitaxial layer arranged over a first surface of the substrate. A source region having a first conductivity type may be arranged in the epitaxial layer. A well region having a second conductivity type may be laterally adjacent to the source region. The first conductivity type may be different from the second conductivity type. A gate dielectric layer may be arranged over the well region. A field dielectric layer may be arranged over the epitaxial layer adjacent to the well region.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.

A method of manufacturing an electrode of a semiconductor device includes: preparing a semiconductor substrate including an impurity-doped region; forming a first metal layer on the impurity-doped region; forming a second metal layer on the first metal layer; and heating the semiconductor substrate including the first metal layer and the second metal layer, wherein the impurity-doped region contains silicon, wherein the first metal layer contains tantalum, wherein the second metal layer contains titanium, and wherein, by the heating, a first silicide layer containing titanium, tantalum, and silicon is formed on the impurity-doped region, and a second silicide layer containing titanium and silicon is formed on the first silicide layer.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.