A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active portion and a gate pad portion; a first semiconductor layer of the first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has first semiconductor regions of the first conductivity type, first trenches, gate insulating films, first gate electrodes, an interlayer insulating film, and second semiconductor regions of the second conductivity type. The gate pad portion has at least one second trench, an insulating film 9b, at least one second gate electrode, at least one fourth semiconductor region of the second conductivity type, and a gate electrode pad. Between the gate electrode pad and the semiconductor substrate, a polycrystalline silicon film is provided.

A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.

A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.

A semiconductor device includes a substrate including a first active region, a second active region, and an isolation region positioned between the first active region and the second active region; and a gate layer crossing over the first active region, the second active region, and the isolation region, wherein the gate layer includes a first impurity doped portion overlapping with the first active region, a second impurity doped portion overlapping with the second active region, and a diffusion barrier portion positioned between the first impurity doped portion and the second impurity doped portion.

A method for fabricating a semiconductor device may include: forming a gate dielectric material over a substrate; sequentially forming a carbon-undoped polysilicon layer and a carbon-doped polysilicon layer over the gate dielectric material; doping the carbon-doped polysilicon layer with a dopant; forming a columnar crystalline polysilicon layer over the carbon-doped polysilicon layer doped with the dopant; and performing annealing to activate the dopant

A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.

A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.