A gate electrode (3) is provided on a main surface of a silicon substrate (1) via a gate insulating film (2). A source/drain region (4,5) is provided on sides of the gate electrode (3) on the main surface of the silicon substrate (1). A first silicide (6) is provided on an upper face and side faces of the gate electrode (3). A second silicide (7) is provided on a surface of the source/drain region (4,5). No side-wall oxide film is provided on the side faces of the gate electrode (3). The second silicide (7) is provided at a point separated from the gate electrode (3).

In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.

A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.