A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than that of the channel region; a gate insulating layer disposed on the channel region of the oxide semiconductor layer; a gate electrode disposed on the gate insulating layer; and an aluminum oxide layer covering the lateral surface of the gate insulating layer, and the source region and the drain region, wherein the gate insulating layer has a multi-layer structure including a first insulating layer and a second insulating layer, and the first insulating layer contains silicon oxide as a main component, and is disposed on and in contact with the channel region.

Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the conductive levels. The conductive levels have projections above and below the recesses. The projections have outer edges. An outer periphery of an individual conductive level is defined by a straight-line boundary extending from the outer edge of the projection above the recess in the individual conductive level to the outer edge of the projection below the recess in the individual conductive level. A depth of the recess is defined as a horizontal distance from the straight-line boundary to an innermost periphery of the recess. The recesses have depths of at least about 5 nm. Charge-blocking regions extend within the recesses. Charge-storage structures are along the charge-blocking regions. Gate dielectric material is along the charge-storage structures. Channel material is along the gate dielectric material.

An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area. The smaller thickness of the second top spacer being closer to the fin allows dopants to diffuse a shorter distance when forming a junction between the top S/D and the channel of the VFET.

A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode.

A semiconductor device includes an n− type layer on a first surface of the substrate, a p type region on a part of the n− type layer, a gate on the n− type layer and the p type region, a first gate protection layer on the gate and a second gate protection layer on the first gate protection layer, a source on the second gate protection layer and the p type region, and a drain on the second surface of the substrate.