According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first insulating member, and a compound member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating region. The first insulating region is between the third partial region and the first electrode portion. The compound member includes a first compound region. At least a part of the first semiconductor portion dose not overlap the compound member in the second direction.

A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

According to one embodiment, a semiconductor device includes first to fifth electrodes, a semiconductor member, a first insulating member, and first and second connecting members. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The fifth electrode includes a first electrode region. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to seventh partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first, second, and third semiconductor portions. The first insulating member includes a first insulating region. The first connecting member electrically connects the fifth electrode with the first electrode. The second connecting member electrically connects the fourth electrode with the third electrode.

Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

A semiconductor device includes first and second n-type transistors and first and second p-type transistors. The first n-type transistor includes a first channel layer and a first portion of a high-k dielectric layer over the first channel layer. The second n-type transistor includes a second channel layer and a second portion of the high-k dielectric layer over the second channel layer, wherein the second portion includes a higher amount of an n-type dipole material than the first portion. The first p-type transistor includes a third channel layer and a third portion of the high-k dielectric layer over the third channel layer. The second p-type transistor includes a fourth channel layer and a fourth portion of the high-k dielectric layer over the fourth channel layer, wherein the fourth portion includes a higher amount of a p-type dipole material than the third portion.

A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.