Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.

A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

Some embodiments include a floating body transistor which has a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base. A region between the upwardly-projecting sidewalls is an interior region of the bracket. The interior region of the bracket has an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls. The sidewalls are a first sidewall and a second sidewall. The first and second sidewalls have first and second notches, respectively, which extend downwardly into the first and second sidewalls. The first and second notches are horizontally aligned with one another. Dielectric material lines the interior surface of the bracket. A semiconductor material body is within the interior region of the bracket and along the dielectric material. The semiconductor material body has a third notch which is horizontally aligned with the first and second notches.

A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active region of the substrate and includes a plurality of memory cells, each of which includes a transistor. The transistor has a nano-scaled pillar that extends substantially vertically from the continuous active region of the substrate.

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.

A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.