A method of manufacturing an optoelectronic semiconductor chip includes a) providing a semiconductor layer sequence having an active region that generates or receives radiation on a substrate; b) forming at least one recess extending through the active region; c) forming a metallic reinforcement layer on the semiconductor layer sequence by galvanic deposition, the metallic reinforcement layer completely covering the semiconductor layer sequence and at least partially filling the recess; and d) removing the substrate, wherein the metallic reinforcement layer is leveled on a side facing away from the semiconductor layer sequence.

A solar cell including a semiconductor substrate having a first conductivity type an emitter region, having a second conductivity type opposite to the first conductivity type, on a first main surface of the semiconductor substrate an emitter electrode which is in contact with the emitter region a base region having the first conductivity type a base electrode which is in contact with the base region and an insulator film for preventing an electrical short-circuit between the emitter region and the base region, wherein the insulator film is made of a polyimide, and the insulator film has a C.sub.6H.sub.11O.sub.2 detection count number of 100 or less when the insulator film is irradiated with Bi.sub.5.sup.++ ions with an acceleration voltage of 30 kV and an ion current of 0.2 pA by a TOF-SIMS method. The solar cell can have excellent weather resistance and high photoelectric conversion characteristics.

A protection method for through-holes of a semiconductor wafer having the steps: providing a semiconductor wafer, and comprising a plurality of solar cell stacks, wherein each solar cell stack has a Ge substrate forming a bottom side of the semiconductor wafer, a Ge subcell, and at least two III-V subcells in the order mentioned, as well as at least one through-hole, extending from the top side to the bottom side of the semiconductor wafer, with a continuous side wall and a circumference that is oval in cross section; applying a photoresist layer to a top side of the semiconductor wafer and to at least one region of the side wall of the through-hole, said region adjoining the top side, and applying an organic filler material by means of a printing process to a region of the top side, said region comprising the through-hole, and into the through-hole.

Dual-depth through-wafer-via semiconductor devices and methods for fabricating dual-depth through-wafer-via semiconductor devices are disclosed. In particular, back-contact-only multijunction photovoltaic cells and the process flows for making such cells are disclosed. The dual-depth through-wafer-via multijunction photovoltaic cells include through-wafer-vias for interconnecting the front surface epitaxial layer to a contact pad on the back surface. Before etching the through-wafer-vias the substrate is thinned to less than 150 pm. The dual-depth through-wafer-vias are formed using a two-step wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers. Low-stress passivation layers are used to reduce the thermo-mechanical stress of the semiconductor devices. A bypass diode is integrated in the recess on the backside formed by the dual-depth through-wafer structure.

A stacked multi-junction solar cell with a front side contacted through the rear side and having a solar cell stack having a Ge substrate layer, a Ge subcell, and at least two III-V subcells, with a through contact opening, a front terminal contact, a rear terminal contact, an antireflection layer formed on a part of the front side of the multi-junction solar cell, a dielectric insulating layer, and a contact layer. The dielectric insulating layer covers the antireflection layer, an edge region of a top of the front terminal contact, a lateral surface of the through contact opening, and a region of the rear side of the solar cell stack adjacent to the through contact opening. The contact layer from a region of the top of the front terminal contact that is not covered by the dielectric insulating layer through the through contact opening to the rear side.

Surface mount semiconductor devices and methods for fabricating surface mount semiconductor devices are disclosed. In particular, back-contact-only multijunction photovoltaic cells and the process flows for making such cells are disclosed. The surface mount multijunction photovoltaic cells include through-wafer-vias for interconnecting the front surface epitaxial layer to a contact pad on the back surface. Before etching the through-wafer-vias the substrate is thinned to less than 150 μm. The through-wafer-vias are formed using a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers. Low stress passivation layers are used to reduce the thermo-mechanical stress of the semiconductor devices.

A solar cell including a semiconductor substrate having a first conductivity type an emitter region, having a second conductivity type opposite to the first conductivity type, on a first main surface of the semiconductor substrate an emitter electrode which is in contact with the emitter region a base region having the first conductivity type a base electrode which is in contact with the base region and an insulator film for preventing an electrical short-circuit between the emitter region and the base region, wherein the insulator film is made of a polyimide, and the insulator film has a C.sub.6H.sub.11O.sub.2 detection count number of 100 or less when the insulator film is irradiated with Bi.sub.5.sup.++ ions with an acceleration voltage of 30 kV and an ion current of 0.2 pA by a TOF-SIMS method. There can be provided a solar cell having excellent weather resistance and high photoelectric conversion characteristics.

Improved high work function back contacts for solar cells are provided. In one aspect, a method of forming a solar cell includes: forming a completed solar cell having a substrate coated with an electrically conductive material, an absorber disposed on the electrically conductive material, a buffer layer disposed on the absorber, a transparent front contact disposed on the buffer layer, and a metal grid disposed on the transparent front contact; removing the substrate and the electrically conductive material using exfoliation, exposing a backside surface of the solar cell; depositing a high work function material onto the back side surface of the solar cell; and depositing a back contact onto the high work function material. A solar cell formed by the present techniques is also provided. Yield of the exfoliated device can be improved by removing bubbles from adhesive used for exfoliation and/or forming contact pads to access the metal grid.

A photovoltaic or light detecting device is provided that includes a periodic array of dome or dome-like protrusions at the light impingement surface and three forms of reflector/back electrode at the device back. The beneficial interaction between an appropriately designed top protrusion array and these reflector/electrode back contacts (R/EBCs) serve (1) to refract the incoming light thereby providing photons with an advantageous larger momentum component parallel to the plane of the back (R/EBC) contact and (2) to provide optical impedance matching for the short wavelength incoming light. The reflector/back electrode operates as a back light reflector and counter electrode to the periodic array of dome or dome-like structures. A substrate supports the reflector/back electrode.

A two-step hole etching method including: providing a semiconductor wafer which has a plurality of solar cell stacks and performing a first and a second processing step. In the first processing step, a first resist layer is applied to a top surface of the semiconductor wafer, at least a first opening is produced in the first resist layer and, via a first etching process, a hole which extends beyond a p/n junction of the Ge sub-cell into the semiconductor wafer is produced in the area of the first opening. In the second process step a second resist layer is applied to the top surface of the semiconductor wafer, a second opening greater than the first opening and surrounding the hole is produced in the second resist layer, and, the hole is widened in an area which extends to the Ge sub-cell serving as an etch stop layer.