A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p− type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p− type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p− type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p− type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p− type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.

Provided is a photodetector including a substrate, a first doped region on the substrate, a second doped region having a ring structure, wherein the second doped region is provided in the substrate, surrounds the first doped region and is horizontally spaced apart from a side of the first doped region, an optical absorption layer on the first doped region, a contact layer on the optical absorption layer, a first electrode on the contact layer, and a second electrode on the second doped region.

An avalanche photo-diode (APD) circuit includes a first APD and a bias circuit. The first APD is configured to detect light. The bias circuit is configured to control a gain of the first APD. The bias circuit includes a second APD, a reference voltage source, a bias voltage generation circuit, and a metal layer configured to shield the second APD from the light. The reference voltage source is configured to bias the second APD. The bias voltage generation circuit is configured to generate a bias voltage for biasing the first APD based on dark current output by the second APD.

A device that detects single optical and radiation events and that provides improved blue detection efficiency and lower dark currents than prior silicon SSPM devices. The sensing element of the devices is a photodiode that may be used to provide single photon detection through the process of generating a self-sustained avalanche. The type of diode is called a Geiger photodiode or signal photon-counting avalanche diode. A CMOS photodiode can be fabricated using a “buried” doping layer for the P-N junction, where the high doping concentration and P-N junction is deep beneath the surface, and the doping concentration at the surface of the diode may be low. The use of a buried layer with a high doping concentration compared to the near surface layer of the primary P-N junction allows for the electric field of the depletion region to extend up near the surface of the diode. With a low doping concentration through the bulk of the diode, the induced bulk defects are limited, which may reduce the dark current. The resulting structure provides a diode with improved quantum efficiency and dark current.

Provided is a backside illuminated avalanche photodiode and a manufacturing method thereof. The backside illuminated avalanche photodiode comprises a semiconductor substrate; a semiconductor structure including a first semiconductor layer being arranged on a front surface of the semiconductor substrate and including a first conductivity type bottom electrical contact layer, a light absorption layer, and a multiplication layer, and a second semiconductor layer, stacked on the first semiconductor layer and including an etch stop layer and a second conductivity type top electrical conductivity layer stacked on the etch stop layer; a plurality of V-grooves in parallel with each other being formed by etching the top electrical contact layer; and a reflective top electrode formed by depositing a multi layer thin metal films on the top electrical contact layer wherein plurality of V-grooves parallel with each other are formed.

The invention relates to a method of fabrication of a photonic chip 1 comprising an avalanche photodiode 20 of the SACM type optically coupled to an integrated waveguide 40, comprising a step for forming a first spacer 24 allowing a constant peripheral recessing dr.sub.zc of the charge region 23 to be defined later on with respect to an edge of the multiplication portion 22, then a step for forming a second spacer 26 allowing a constant peripheral recessing dr.sub.pa of the absorption portion 27 to be defined later on with respect to an edge of the charge region 23.

Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. A photonic device may include a silicon-on-insulator (SOI) substrate with a buried oxide (BOX) layer therein, a Si waveguide and an n-type contact layer formed on the BOX layer, a Si multiplication layer disposed on the n-type contact layer, a p-type Si charge layer disposed on the Si multiplication layer, a germanium (Ge) absorption layer disposed on the p-type Si charge layer, a p-type contact layer disposed on the Ge absorption layer, and a metal layer disposed on the p-type contact layer. A compensated region may be formed between the p-type Si charge layer and the Ge absorption layer with a portion of the compensated region in the p-type Si charge layer and another portion of the compensated region in the Ge absorption layer.

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×10.sup.16 cm.sup.−3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

A photodetector according to an embodiment includes: a first semiconductor layer; a porous semiconductor layer disposed on the first semiconductor layer; and at least one photo-sensing element including a second semiconductor layer of a first conductivity type disposed in a region of the porous semiconductor layer and a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer.

A low voltage APD is disposed at an end of a waveguide extending laterally within a silicon device layer of a PIC chip. The APD is disposed over an inverted re-entrant mirror co-located at the end of the waveguide to couple light by internal reflection from the waveguide to an under side of the APD. In exemplary embodiments, a 45°-55° facet is formed in the silicon device layer by crystallographic etch. In embodiments, the APD includes a silicon multiplication layer, a germanium absorption layer over the multiplication layer, and a plurality of ohmic contacts disposed over the absorption layer. An overlying optically reflective metal film interconnects the plurality of ohmic contacts and returns light transmitted around the ohmic contacts to the absorption layer for greater detector responsivity.