Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Due to size and cost, it becomes advantageous for integrated circuit (IC) manufacturers to use single-ended (one signal path per unique information path) high speed signals electrical contact pins (pins transmitting digital information that connect the integrated circuit to a printed circuit board) with a minimum number of surrounding powers and grounds. This lower cost method, however, creates electrical interference and coupling issues known as crosstalk between two adjacent signal paths in the via structure required to electrically connect the integrated circuit to the signal paths in the printed circuit board. Such crosstalk, in turn, increases jitter, degrades timing, and ultimately reduces the maximum operating speed of the circuit (performance). This disclosure presents a structure using micro-plating, micro-drilling and micro-machining methods that isolates adjacent signals by placing a metal barrier that shunts coupling currents to ground. The micro-drilling methods also reduce the length of adjacent signal paths in a specific signal routing and controlled depth drilling sequence.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

An electronic device is provided. In particular, the electronic device includes (i) an electronic integrated circuit (IC) chip, (ii) a chip mounting substrate for mounting the electronic IC chip on a chip side of the chip mounting substrate, (iii) a radio frequency (RF) interface component disposed on an opposing side of the chip mounting substrate, the opposing side opposing the chip side, and (iv) an RF bridge component penetrating a first opening in the chip mounting substrate and configured to operably connect the electronic IC chip and the RF interface component.

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

An electronic device is provided. In particular, the electronic device includes (i) an electronic integrated circuit (IC) chip, (ii) a chip mounting substrate for mounting the electronic IC chip on a chip side of the chip mounting substrate, (iii) a radio frequency (RF) interface component disposed on an opposing side of the chip mounting substrate, the opposing side opposing the chip side, and (iv) an RF bridge component penetrating a first opening in the chip mounting substrate and configured to operably connect the electronic IC chip and the RF interface component.

A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

The present disclosure describes various embodiments of systems, apparatuses, and related methods for a coaxial through-substrate-via (cx-TSV) based on a Cu/Co metaconductor. One such apparatus comprises a substrate; and a coaxial structure having an outer conductor and a metaconductor for its inner conductor, wherein the coaxial structure extends through the substrate.