Integrated circuit (IC) package employing on-package tunable inductor formed in redistribution layer (RDL) for impedance tuner circuit, and related methods. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. To reduce the circuit area, the tunable inductor is formed in a RDL of a package substrate of the IC package. The IC package also includes a semiconductor die (die) that includes other components of the impedance tuner circuit that are coupled to the tunable inductor by the die being coupled to the package substrate. In this manner, by the tunable inductor being formed in a RDL in the package substrate, the signal path lengths between the tunable inductor and other components of the tunable impedance circuit are reduced, thereby reducing inductance path resistance and improving quality (Q) factor of the tunable inductor.

In an aspect, an integrated circuit (IC) includes a photoimageable dielectric (PID), a transmission line disposed within the PID, and at least one continuous conductive shield disposed within the PID to reduce leakage of a signal transmitted along the transmission line beyond a space defined by at least one continuous conductive shield. In an aspect, the transmission line is a horizontal transmission line, and a first continuous conductive shield is disposed along a first side of the horizontal transmission line and a second continuous conductive shield is disposed along a second side opposite the first side of the horizontal transmission line. In an aspect, the transmission line is a vertical transmission line, and the continuous conductive shield is a cylindrical conductive shield concentric about the vertical transmission line.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.

An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

A semiconductor structure includes a first wiring region including interconnected first metal lines and first vias; an insulator outward of same; and a first circuitry element, located in the insulator, and connected to at least a first one of the first vias. A coaxial through dielectric via is located in the insulator, which includes an inner conductor, a dielectric layer surrounding the inner conductor, and an outer conductor outward of the dielectric layer. The outer conductor includes inner and outer footing structures. A second wiring region is outward of the insulator, and includes a signal line connected to the inner conductor and a power line connected to the outer footing structure. The inner conductor is connected to at least a second one of the first vias and the inner footing structure is connected at least a third one of the first vias.