A semiconductor package including a semiconductor chip, and a package structure configured to accommodate the semiconductor chip, and a manufacturing method thereof are disclosed. The package structure includes a substrate having one surface and the other surface opposite to the one surface, at least one conductive via extending through one surface and the other surface of the substrate, a wiring layer formed at one surface of the substrate, to transmit an electrical signal, a chip accommodating portion formed through removal of a portion of the substrate from the other surface toward the one surface, and a contact pad connected to the wiring layer and formed to be exposed through the chip accommodating portion. The semiconductor chip is inserted into the chip accommodating portion and is connected to the contact pad. Since the semiconductor chip is mounted after formation of the package structure, yield of the semiconductor package increases.

A module package in which electronic components are packaged. The package module may comprise a base, at least one component, a housing, and a coaxial lead assembly. The component is over the base. The housing is over the base and encompasses the component. The coaxial lead assembly extends out of the housing and facilitates electrical connections with the component. The at least one coaxial lead assembly comprises a dielectric structure, a central conductor, and an outer conductor formed by a top wall extending between two side walls. The central conductor may be between the two side walls. The dielectric structure may reside between the central conductor and the outer conductor, such that the central conductor and outer conductor are isolated from one another.

A semiconductor package structure is provided. The structure includes a package substrate having a first surface and a second surface opposite to the first surface and including a ground layer embedded therein. A semiconductor die is formed on the first surface of the package substrate and an antenna pattern layer is formed on the second surface of the package substrate and electrically coupled to the semiconductor die. The structure also includes a first connector and a second connector formed on the second surface of the package substrate and arranged adjacent to the antenna pattern layer. The first connector is electrically coupled to the semiconductor die and electrically isolated to the ground layer, and the second connector is electrically coupled to the ground layer. A wireless communication device including the semiconductor package structure is also provided.

Embodiments disclosed herein include die modules, electronic packages, and systems. In an embodiment, a die module comprises a first substrate and a first die over the first substrate. In an embodiment, the die module further comprises a second die over the first substrate adjacent to the first die. In an embodiment, the die module further comprises a via module through the first substrate. In an embodiment, the via module comprises a second substrate, where the second substrate comprises glass, and a via through the second substrate.

Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

An antenna substrate includes: a first insulating layer surrounding a cavity; a second insulating layer of which at least a portion is disposed in the cavity and containing an insulating material different from an insulating material of the first insulating layer; a first patch antenna having one surface facing the first insulating layer by an amount greater than half of an area of the first patch antenna; and a second patch antenna having one surface facing the cavity by an amount greater than half of an area of the second patch antenna.

A transformer balun fabricated in silicon and including a series of alternating metal layers and dielectric layers that define first and second outer conductors that are part of a coaxial structure. Each dielectric layer includes a plurality of conductive vias extending through the dielectric layer to provide electrical contact between opposing metal layers, where a top metal layer forms a top wall of each outer conductor and a bottom metal layer forms a bottom wall of each outer conductor and the other metal layers and the dielectric layers define sidewalls of the outer conductors. Inner conductors extends down both of the first and second outer conductors and a first output line is electrically coupled to a sidewall of the first outer conductor and a second output line is electrically coupled to a sidewall of the second outer conductor.

A device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip. The device includes an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection includes a section extending in a direction vertical to the main surface of the semiconductor chip. The device further includes an electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection includes a section extending in a direction parallel to the main surface of the semiconductor chip.

Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.