Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.

A cryptographic device (100) arranged to compute a target block cipher (B.sub.t) on an input message (110), the device comprising a first and second block cipher unit (121, 122) arranged to compute the target block cipher (B.sub.t) on the input message, and a first control unit (130) arranged to take the first block cipher result and the second block cipher result as input, and to produces the first block cipher result only if the block cipher results are equal.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure.

The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure.

A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.

A multi-wavelength integrated device (5) including plural semiconductor lasers (6) and plural modulators (7) modulating output beams of the plural semiconductor lasers (6) respectively is mounted on the stem (1). Plural leads (10) penetrates through the stem (1) and are connected to the plural semiconductor lasers (6) and the plural modulators (7) respectively. Each lead (10) is a coaxial line in which plural layers are concentrically overlapped with one another. The coaxial line includes a high frequency signal line (12) transmitting a high frequency signal to the modulator (7), a GND line (14), and a feed line (16) feeding a DC current to the semiconductor laser (6). The high frequency signal line (12) is arranged at a center of the coaxial line. The GND line (14) and the feed line (16) are arranged outside the high frequency signal line (12).

A semiconductor package is provided. The semiconductor package includes a semiconductor die arranged within a housing of the semiconductor package. The semiconductor die holds a radio frequency circuit and a plurality of first electrical contacts. Additionally, the semiconductor package includes a plurality of second electrical contacts formed on the exterior of the housing to enable external electrical contacting of the semiconductor package. The semiconductor package further includes a plurality of transmission lines formed in or on a substrate of the semiconductor package. Each of the plurality of transmission lines couples a respective one of the plurality of first electrical contacts with a respective one of the plurality of second electrical contacts. At least one of the plurality of transmission lines is formed as a stepped transmission line transformer comprising a plurality of transmission line segments exhibiting different impedances to match a respective first impedance of the respectively coupled first electrical contact to a respective second impedance at the respectively coupled second electrical contact. The plurality of transmission line segments exhibit different spacings to one or more ground plane of the semiconductor package.