A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.

Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.

A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a first surface on which a first electrical contact and a second electrical contact are arranged; arranging a protection diode on the first contact and the second contact; galvanically growing a first pin on the first electrical contact and a second pin on the second electrical contact; and embedding the first pin, the second pin, and the protection diode in a molded body.

A method of producing an optoelectronic component includes providing an optoelectronic semiconductor chip having a first surface on which a first electrical contact and a second electrical contact are arranged; arranging a protection diode on the first contact and the second contact; galvanically growing a first pin on the first electrical contact and a second pin on the second electrical contact; and embedding the first pin, the second pin, and the protection diode in a molded body.

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die, which includes one or more extended bond pads, a package comprising a base and a lid, and a plurality of new bond wires. The modified extracted die is placed into a cavity of the base. After the modified extracted die is placed into the cavity, the plurality of new bond wires are bonded between the one or more extended bond pads of the modified extracted die and package leads of the package base or downbonds. After bonding the plurality of new bond wires, the lid is sealed to the base.

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die, which includes one or more extended bond pads, a package comprising a base and a lid, and a plurality of new bond wires. The modified extracted die is placed into a cavity of the base. After the modified extracted die is placed into the cavity, the plurality of new bond wires are bonded between the one or more extended bond pads of the modified extracted die and package leads of the package base or downbonds. After bonding the plurality of new bond wires, the lid is sealed to the base.

Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.