Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, hybrid manufacturing refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Disclosed herein is a semiconductor device that includes a substrate having a conductive circuit and a first mold material encapsulating the conductive circuit, the first mold material configured to function as an electrical insulator. The semiconductor device further includes a semiconductor die encapsulated with the first mold material or a second mold material. Further disclosed is a method of making a semiconductor device.

Disclosed herein is a releasable carrier that includes a supporting carrier, a carrier conductive layer, and a releasable tape located between the supporting carrier and the carrier conductive layer. The releasable tape attaches the supporting carrier to the carrier conductive layer. The releasable tape is configured to release the supporting carrier from the carrier conductive layer after being exposed to an activating source. The releasable carrier further includes a thin conductive layer attached to the carrier conductive layer, the thin conductive layer creating a surface configured to receive a conductive circuit. Further disclosed is a method for fabricating the releasable carrier and a method for making a semiconductor device using the releasable carrier.

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die is attached to the second surface. The substrate includes a layer of insulative material and at least a portion of an embedded conductive circuit in the layer of insulative material. The substrate includes an etched layer of a conductive material attached to the portion of the conductive circuit, the etched layer of the conductive material located on the first surface of the substrate.

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.

Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, hybrid manufacturing refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.