An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Various aspects of the present disclosure generally relate to wireless communication, and to a pillar that includes one or more structures configured to define a capacitor. For example, a device includes a die, a substrate, and a pillar having an embedded capacitor. The pillar is electrically connected to one or more conductors of the die and to one or more conductors of the substrate. The pillar includes a first conductive structure and a second conductive structure. The pillar also includes a dielectric layer disposed between the first conductive structure and the second conductive structure to define the embedded capacitor.