An assembly may include a base element comprising a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate and including a signal pad to convey an electrical signal to the active circuitry. The assembly may further include a first functional element comprising a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element having a first contact feature to connect to power or ground, wherein the first bonding layer is hybrid bonded to the second bonding layer.

A semiconductor chip includes a semiconductor substrate, an insulation layer positioned on the semiconductor substrate and that includes a plurality of via holes, and a bump positioned within the plurality of via holes and on the insulation layer. Portions of the bump positioned within the plurality of via holes are connected to each other.

A method includes: forming a first photoresist layer on a first insulating layer; forming a first photoresist pattern having first opening patterns using a first exposure mask; etching the first insulating layer using the first photoresist pattern to form first via holes; removing the first photoresist pattern; forming a second photoresist layer on the first insulating layer; forming a second photoresist pattern having second opening patterns using a second exposure mask; etching the first insulating layer using the second photoresist pattern to form second via holes; removing the first photoresist pattern; forming a redistribution wiring layer on the first insulating layer, the redistribution wiring layer having first redistribution wirings connected to first bonding pads under the first insulating layer through the via holes; and mounting a semiconductor chip on the redistribution wiring layer, the semiconductor chip comprising chip pads connected to the first redistribution wirings.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (CTE) of less than 10 parts per million per degree Celsius (ppm/ C.). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers, and a first coil, a second coil, and a third coil which are formed above the semiconductor substrate. In a region located under the first coil and overlapping the first coil in plan view, the second and third coils CL2a and CL2b are disposed. The second and third coils are foamed in the same layer and electrically coupled in series to each other. Each of the second and third coils and the first coil are not coupled to each other via a conductor, but are magnetically coupled to each other.