To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

A sensor package comprising a lead frame, a current sensor die, and an interposer. The lead frame includes: (i) a primary conductor, (ii) a plurality of secondary leads, and (iii) a layer of dielectric material that is disposed between the primary conductor and the plurality of secondary leads. The current sensor die includes one or more sensing elements. The current sensor die is configured to measure a level of electrical current through the primary conductor of the lead frame. The interposer is disposed over the layer of dielectric material. The interposer includes a plurality of conductive traces that are configured to couple each of a plurality of terminals of the current sensor die to a respective one of the plurality of secondary leads.

A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

Electronic device packages that include one or more circuit substrates, one or more cavities defined by a cover separated from a circuit substrate by an interposer substrate with an aperture disposed above the circuit substrate can be formed by panel-level fabrication processes in which multiple assemblies are formed by singulating a larger panel assembly formed by multiples panels bonded to each other. A panel that includes multiple levels is partially diced to form channels which are filled with molding material. The subsequent structure is diced again to singulate individual stacked packages that include a portion of the molding material surrounding one or more interposers. The molding material can seal gaps between an interposer and a circuit substrate to which it is bonded, as well as providing electrical isolation between electrical interconnects that would otherwise be exposed at edges of each package.

Embodiments of the subject matter described herein relate semiconductor chip packages, and more specifically, to Quad Flat No-Lead (QFN) burr free dimple packages, Small Outline No-lead (SON) burr free and defect free dimple packages, and a process scheme for producing a burr free dimple after singulation without additional deburring processes.

Example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. An example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.

A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over a first surface of the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. A conductive via is formed through the second substrate. An IPD is formed over a second surface of the second substrate. The IPD is electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.

A method of manufacturing a semiconductor device includes: forming a primary side electrode on a substrate; forming an insulating layer on the substrate and the primary side electrode; forming a secondary side electrode facing the primary side electrode with the insulating layer in between and magnetically or capacitively connected to the primary side electrode on the insulating layer; forming an opening part at the insulating layer by etching to expose part of the primary side electrode; and bonding wiring to the primary side electrode exposed through the insulating layer at the opening part, wherein at least one step is formed on a sidewall of the opening part by performing the etching in a plurality of processes.