Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

Wafer-scale integration has been a goal of chip manufacturers because of their promise to provide superior computing hardware at lower costs compared to conventional chip manufacturing techniques. Various technical difficulties have made wafer-scale chips impractical or uneconomical to produce. Proposed are systems and methods for achieving wafer-scale integration by utilizing bridge dies to create electrical connections. In one embodiment, semiconductor wafers and printed die grids using standard fabrication (e.g., lithography equipment) can be made into wafer-scale ICs.

Existing methods of cooling computer chips can be inefficient, when applied to high density computing systems, such as wafer-scale-integrated (WSI) systems and other high-density computing systems. In particular, current methods of cooling integrated circuits can be inefficient when applied to high-density computing systems, as the cooling medium can lose its ability to absorb heat due to heat absorption and aggregation when the cooling medium travels through multiple surfaces and regions of a high-density computing system. In some embodiments, systems and methods of achieving high-density computing, by using bridge dies and standard and/or WSI lithography techniques are disclosed. In other embodiments, systems and methods of cooling high-density computing systems are disclosed. Two-phase immersion cooling that avoids heat aggregation is used.

A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

An interposer layer includes an integral waveguide to facilitate high speed (e.g., greater than 80 GHz) communication between semiconductor dies in a semiconductor package. An interposer layer may include a waveguide member and a dielectric layer disposed adjacent at least a portion of an exterior perimeter of the waveguide member. The waveguide member includes a material having a first relative permittivity. The dielectric member includes a material having a second relative permittivity that is less than the first relative permittivity. The waveguide member and the dielectric member form an interposer layer having an upper surface and a lower surface. A first conductive sheet may be disposed proximate the upper surface of the interposer layer and a second conductive sheet may be disposed proximate the lower surface of the interposer layer.

A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device.

A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.

Method and Apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes first and second inductors. The first semiconductor chip transmits a first combination of a plurality of data bits in logical value by flowing a first current through the first inductor and by flowing substantially no current through the second inductor. The second semiconductor chip includes third and fourth inductors that correspond respectively to the first and second inductors of the first semiconductor chip. The second semiconductor chip receives the first combination of the plurality of data bits in logical value by detecting an electromotive force at the third inductor responsive to the first current and by detecting substantially no electromotive force at the fourth inductor responsive to no current.

A semiconductor device includes a first semiconductor element, a first connection terminal formed on a lower surface of the first semiconductor element, a second semiconductor element mounted on the lower surface of the first semiconductor element so that the second semiconductor element partially overlaps the first semiconductor element in plan view, a second connection terminal formed on a lower surface of the second semiconductor element, and a wiring substrate on which the first and second semiconductor elements are mounted. The wiring substrate includes first and second connection pads electrically connected to the first connection terminal and the second connection terminal, respectively. The semiconductor device further includes a third connection terminal formed on the first connection pad and electrically connected to the first connection terminal. One of the first connection terminal and the third connection terminal is a metal post, and the other is a solder ball.

An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.