The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal. The second semiconductor chip contains: a reception coil whereby the magnetic field signal converted by the transmission coil is converted into a reception signal; and a reception unit reconstructing, on the basis of the state of the reception signal, the data that has been transmitted.

Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

A blade computing system is described with a wireless communication between blades. In one embodiment, the system includes a first blade in the enclosure having a radio transceiver to communicate with a radio transceiver of a second blade in the enclosure. The second blade has a radio transceiver to communicate with the radio transceiver of the first blade. A switch in the enclosure communicates with the first blade and the second blade and establishes a connection through the respective radio transceivers between the first blade and the second blade.

A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil.

According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.

Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.