An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.

A signal transmission device provided with an insulated chip. The insulated chip includes: an element insulating layer; and a first insulated element and a second insulated element which are provided in the element insulating layer. The first insulated element includes a first front-surface-side electrically conductive portion and a first back-surface-side electrically conductive portion. The second insulated element includes a second front-surface-side electrically conductive portion and a second back-surface-side electrically conductive portion. The first back-surface-side electrically conductive portion and the second back-surface-side electrically conductive portion are electrically connected to each other. The first front-surface-side electrically conductive portion is electrically connected to a primary-side circuit via the first pad. The second front-surface-side electrically conductive portion is electrically connected to a secondary-side circuit via the second pad.

An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.

A semiconductor device assembly can include an assembly semiconductor die having a top surface with a first and a second assembly communication element thereat. The semiconductor device assembly can further include a semiconductor die stack coupled to the top surface. The die stack can include a first and a second semiconductor die, each having a top surface perpendicular to the top surface of the assembly semiconductor die. Further, the first semiconductor die can have a first die communication element aligned with and configured to directly communicate with the first assembly communication element, and the second semiconductor die can have a second die communication element aligned with and configured to directly communicate with the second assembly communication element.

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a first semiconductor die and a second semiconductor die stack structure. A first wireless communication portion is formed in the first semiconductor die. The second semiconductor die stack structure includes a first die stack structure and a second die stack structure. A second wireless communication portion and a third wireless communication portion are respectively formed in two sides, along a second direction, of the first die stack structure. A fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure. The first direction is a direction parallel to a plane of the first semiconductor die, and the second direction is a direction perpendicular to the plane of the first semiconductor die.

Provided are semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a first base; a first semiconductor chip connected to the first base; a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on an outermost side of the second semiconductor chips in the first direction, in which the first direction is a direction parallel to a plane of the first base; and at least one second base, signal lines in the at least one second base being connected to the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

Embodiments provide a method for manufacturing a microelectronic arrangement. The method includes a step of providing a chip-film module with a semiconductor chip and a film substrate having arranged thereon the semiconductor chip, wherein the chip-film module includes at least one coupling element spaced apart from the semiconductor chip and electrically coupled to at least one terminal of the semiconductor chip. Furthermore, the method includes a step of embedding the chip-film module into a printed circuit board, wherein, in embedding the chip-film module into the printed circuit board, the at least one coupling element of the chip-film module is coupled vertically [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the printed circuit board] to at least one coupling counter element of the printed circuit board.

The instant disclosure includes a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator and a method for manufacturing the same. The method includes a leadframe providing step, a chip connecting step and a coil alignment step. The leadframe providing step includes providing a first and a second leadframe each including a chip carrying portion, a coil portion, a plurality of pins and floating pins. The chip connecting step includes disposing at least a first chip and at least a second chip onto the corresponding chip carrying portions for electrically connecting the chips to the pins. The coil alignment step includes arranging the first leadframe above or beneath the second leadframe and applying a first and a second magnetic field to the first and the second leadframes respectively for aligning the coil portions, thereby controlling the coupling effect between two coil portions.

A control system (100, 200) and method (300) are provided where a first voltage domain circuit (111) and a power switch (121) operate in a first voltage domain and where a second voltage domain circuit (109) operates in a second voltage domain, where the second voltage domain circuit includes a gate driver circuit (202) for providing a control terminal driving signal (PWM1) to drive the power switch, and also includes a watchdog communication circuit (207) for scheduling watchdog communications between the first and second voltage domain circuits to be temporally separated from noise-inducing signal transitions in the control terminal driving signal.