A transformer chip of a signal transmitting device has a substrate, an element insulation layer, and a first transformer and a second transformer provided within the element insulation layer. The first transformer comprises a first coil, and a second coil positioned facing the first coil in the z direction. The second transformer comprises a first coil, and a second coil positioned facing the first coil in the z direction. The second coil of the first transformer and the second coil of the second transformer are electrically connected. The transformer chip comprises a back surface insulating layer provided on the back surface of the substrate.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

In certain embodiments, an assembly has intermediate pods magnetically, but not galvanically, coupled along an electrically conductive cable. Each pod has a magnetic core surrounding and inductively coupled to the cable and one or more coils inductively coupled to the magnetic core. The pod transmits, for example, outgoing current pulses on the cable by inducing electrical signals in the cable using a transmitter coil and the magnetic core. In addition, the pod repeats, for example, incoming current pulses on the cable by inducing electrical signals in the cable using the transmitter coil and the magnetic core, based on electrical signals induced in a receiver coil via the magnetic core by the incoming current pulses. Such an assembly can function as a data collection system for scientific research and/or as an early-warning system for events, such as earthquakes and tsunamis, without having to modify the cable itself.

A semiconductor device includes multiple semiconductor chips and a control unit. Each of the semiconductor chips has multiple signal processing units that can be connected with each other, multiple in-chip signal lines that are respectively connected to the signal processing units and that can be connected with each other, and a connection-state changing unit that changes the connection state between the in-chip signal lines according to an instruction from the control unit. The connection-state changing unit of each semiconductor chip changes the connection state between the in-chip signal lines according to the instruction from the control unit, so that the connection state between the signal processing units is changed.

Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.

A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element. The signal transmission/reception coil has: a conductor that is formed inside the insulating layer part; and a conductor that is formed inside the semiconductor substrate part.

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.

A semiconductor package includes a first die, a second die, and a hybrid-type adhesive. The second die is stacked on the first die through the hybrid-type adhesive. The hybrid-type adhesive includes a conductive adhesive and a non-conductive adhesive. The conductive adhesive is disposed between the non-conductive adhesive and the first die. The non-conductive adhesive is disposed between the conductive adhesive and the second die.