An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.

Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.

Stack assembly for radio-frequency applications. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.

A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

A module includes: a substrate including a first main surface; a first component mounted on the first main surface; a first land electrode provided on the first main surface; a first mold resin that covers at least the first main surface and the first component; a top surface shield film that covers a top surface of the first mold resin; a side surface shield film that covers a side surface of the first mold resin; a first conductor pillar provided in the first mold resin to electrically connect the first land electrode and the top surface shield film; and an upper first bypass conductor provided in the first mold resin to electrically connect the top surface shield film and the side surface shield film.

A semiconductor package according to one embodiment comprises a substrate. A semiconductor chip is provided on the substrate. A resin layer is configured to cover the semiconductor chip on the substrate. A metal film is configured to cover a surface and side surfaces of the resin layer. The metal film is a laminated film including first to fourth metal layers. The first metal layer is configured to cover the resin layer. The second metal layer includes a first metal material that is different from a material of the first metal layer. The third metal layer includes an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material. The fourth metal layer is configured to cover the second or third metal layer.