In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.

A composite structure includes a first metal layer, a second metal layer, and a ceramic layer disposed therebetween. The ceramic layer has a first surface and a second surface opposite to each other and is adapted to absorb electromagnetic waves. The absorbance reaction range of the electromagnetic waves by the ceramic layer ranges from 100 MHz to 400 GHz. The first metal layer has an opening exposing the second surface. An inner sidewall of the first metal layer surrounds the opening. The orthographic projection of the second metal layer on the ceramic layer at least partially overlaps the orthographic projection of the opening on the ceramic layer. The thickness ratio of the first metal layer to the second metal layer is 1:1 to 1:2. The area ratio of the first metal layer to the second metal layer is 1:1.2 to 1:4. A package architecture including the composite structure is also provided.

It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.

A semiconductor device includes a plurality of semiconductor chips disposed in a vertical form through a spacer, in which a shield layer having a thickness such that an electromagnetic field radiation generated from a generation source of the semiconductor chip can sufficiently be absorbed is disposed between the semiconductor chips.