In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.

A semiconductor package including a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a ground member disposed on the active surface of the semiconductor chip, and an electromagnetic shielding member passing through the semiconductor chip, electrically connected to the ground member, and covering at least some regions of the non-active surface of the semiconductor chip may be provided.

A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a second integrated circuit die coupled to the first integrated circuit die, and a through-via coupled between a first conductive feature of the first integrated circuit die and second conductive feature of the second integrated circuit die. A conductive shield is disposed around a portion of the through-via.

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

A die package having lead structures connecting to a die that provide for electromagnetic interference reductions. Mixed impedance leads connected to the die have a first lead with a first metal core, a dielectric layer surrounding the first metal core, and first outer metal layer connected to ground; and a second lead with a second metal core, and a second dielectric layer surrounding the second metal core, and a second outer metal layer connected to ground. Each lead reducing susceptibility to EMI and crosstalk.

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.

The present disclosure relates to a stacked device, a manufacturing method, and an electronic instrument, capable of suppressing adverse effects of noise generated from one substrate, onto the other substrate. A first metal layer is formed on a bonding surface of one substrate, and a second metal layer is formed on a bonding surface of the other substrate stacked with the one substrate. Subsequently, an electromagnetic wave shield structure that interrupts an electromagnetic wave between the one substrate and the other substrate is provided by bonding the metal layer of the one substrate with the metal layer of the other substrate and by performing potential fixing. The present technology can be applied, for example, to a stacked CMOS image sensor.

A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.