A radio-frequency module including a mounting substrate that has mounting faces opposed to each other; a PA that is mounted on the mounting face, that is a radio-frequency component, and that has an emitter terminal; a through electrode that is connected to the emitter terminal of the PA and that passes through the mounting faces of the mounting substrate; and a ground terminal connected to the through electrode.

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other.

A semiconductor device has laminated therein three or more chips. The plurality of chips are provided with substrates, transmission coils, and reception coils that are disposed in regions where the transmission coils and the reception coils do not overlap with each other in an in-plane direction of the substrates. The transmission coils are disposed in regions that are in a lamination direction and that are adjacent to and overlap with reception coils of other chips. The reception coils are configured to allow data transmission with respect to the transmission coils that are disposed on the same substrates.

The present invention discloses an SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method thereof. With the SOC PMUT suitable for high-density system integration, vertical stacking and monolithic integration of a SOC PMUT array with CMOS auxiliary circuits is realized by means of direct bonding of active wafers and a vertical multi-channel metal wiring structure; in addition, the extension to the package layer is implemented by means of TSVs, without any bonding mini-pad on the periphery of the array for communication with the CMOS. Thus, the bottleneck of metal interconnections in conventional ultrasonic transducers is overcome, the chip area occupied by metal interconnections in ultrasonic transducers is greatly reduced, the metal wiring length is reduced, thus the resulting adverse effects of an electrical parasitic effect on the performance of the ultrasonic transducer array are reduced.

A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer.

A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.

The present application provides a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package includes a package substrate, a first semiconductor die, a second semiconductor die, a first encapsulant and a second encapsulant. The package substrate has a first side and a second side facing away from the first side, and the second side has a concave recessed from a planar portion of the second side. The first semiconductor die is attached to the first side of the package substrate. The second semiconductor die is attached to a recessed surface of the concave. The first encapsulant covers the first side of the package substrate and encapsulates the first semiconductor die. The second encapsulant fills up the concave and encapsulates the second semiconductor die.