An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element