Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

IC devices with backend memory and electrical feedthrough networks of interconnects between the opposite sides of the IC devices, and associated assemblies, packages, and methods, are disclosed. An example IC device includes a back-side interconnect structure, comprising back-side interconnects; a frontend layer, comprising frontend transistors; a backend layer, comprising backend memory cells and backend interconnects; and a front-side interconnect structure, comprising front-side interconnects. In such an IC device, the frontend layer is between the back-side interconnect structure and the backend layer, the backend layer is between the frontend layer and the front-side interconnect structure, and at least one of the back-side interconnects is electrically coupled to at least one of the front-side interconnects by an electrical feedthrough network of two or more of the backend interconnects.

An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

A semiconductor package is provided. The semiconductor package includes a first structure with a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure with a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer. The pad structure is bonded to and wider than the connection pad. The pad structure includes: an electrode pad disposed on a bottom surface of the recess portion; a solder disposed on the electrode pad and bonded to the connection pad; and a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer. A melting point of the conductive support is higher than a melting point of the solder.