Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip on a first surface of the first semiconductor chip, and a plurality of conductive pillars on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip includes a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip.

A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.

A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.