Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an L shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a C shape and include a tiered portion that projects towards the lateral side of the second casing.

The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.

A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An upper surface of the molding material is recessed from an upper surface of the through via. A dielectric layer is deposited over the through via and the molding material. The dielectric layer has a first upper surface with a first variation in height between a first area disposed over the through via and a second area disposed over the molding material. Exposure processes are performed on the dielectric layer. The dielectric layer is developed. After the developing, the dielectric layer has a second upper surface with a second variation in height between the first area and the second area. The first variation is greater than the second variation.

A surface-mount electronic device includes a body of semiconductor material, and a lead frame that includes a plurality of contact terminals. The plurality of contact terminals is electrically connected to the semiconductor body. The contact terminals are formed of sintered material.

A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.

An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.

A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.