A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.

An electronic device includes a lead frame, a first clip, a second clip, and a plurality of semiconductor devices. The first clip is stacked with the lead frame. The second clip stacked with the first clip and the lead frame. The second clip includes a first protrusion that engages the first clip and secures the second clip to the first clip. The semiconductor devices are conductively coupled to the lead frame via the first clip and the second clip.

Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

A semiconductor package structure includes a first patterned conductive layer including a first conductive pad, a second conductive pad and a first conductive trace disposed between the first conductive pad and the second first conductive pad. The first conductive pad defines a recess. The semiconductor package structure further includes a second patterned conductive layer including a third conductive pad. The semiconductor package structure further includes a first stud bump electrically connecting the first conductive pad of the first patterned conductive layer to the third conductive pad of the second patterned conductive layer. The semiconductor package structure further includes a first encapsulation layer disposed between the first patterned conductive layer and the second patterned conductive layer.

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an L shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a C shape and include a tiered portion that projects towards the lateral side of the second casing.

A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.