Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

An integrated circuit package comprising a heat spreader; one or more substrate(s); one or more standoff(s); and one or more electronic component(s). One or more component(s) is/are coupled to a substrate and the substrate maybe coupled to a heat spreader. Standoff(s) are coupled on the heat spreader or substrates forming a cavity, and one or more component(s) and substrate(s) are located inside the cavity.

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

A wire bonding apparatus includes: a first tensioner which forms, nearer a wire supply side than a bonding tool, a first gas flow for applying a tension toward the wire supply side on a wire; a second tensioner which forms, between the first tensioner and a pressing part of the bonding tool, a second gas flow for applying a tension toward the wire supply side on the wire; and a control part which controls the first tensioner and the second tensioner. The control part implements control, in a predetermined period after a first bonding step for bonding the wire to a first bonding point, to turn off at least the second gas flow of the second tensioner among the first tensioner and the second tensioner or to make at least the second gas flow smaller than in the first bonding step.

A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.

A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices on the first substrate, a lower interconnection structure on the circuit devices, and a lower bonding structure electrically connected to the lower interconnection structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes and extend in the first direction, and an upper bonding structure electrically connected to the gate electrodes and the channel structures and bonded to the lower bonding structure. The second semiconductor structure further includes a first via connected to an upper portion of the second substrate, a second via spaced apart from the first via and the second substrate, and a contact plug.

A semiconductor device including a substrate; a horizontal conductive layer disposed on the substrate; a support layer disposed on the horizontal conductive layer; a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the support layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes; a channel structure penetrating through the stack structure; a separation structure penetrating through the horizontal conductive layer, the support layer, and the stack structure and extending in a first direction; and a conductive pattern disposed on a level between the horizontal conductive layer and a lowermost interlayer insulating layer, among the plurality of interlayer insulating layers, and protruding outwardly of the separation structure from a side surface of the separation structure.

A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.