A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.

Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.

A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.

An integrated circuit package comprising one or more electronic component(s); and one or more substrate(s), including a first substrate and a second substrate, wherein said first substrate including a first cavity on a first surface of said first substrate and a second cavity on a second surface of said first substrate, said second substrate includes a third cavity on a first surface of said second substrate and a fourth cavity on a second surface of said second substrate, said first substrate and said second substrate are stacked and coupled, and said one or more electronic component(s) is/are disposed inside said first cavity of first substrate and said fourth cavity of second substrate.

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

A packaged integrated circuit device includes a frame having a cavity therein and an inner semiconductor chip within the cavity. A lower re-distribution layer is provided, which extends adjacent lower surfaces of the frame and the inner semiconductor chip. The lower re-distribution layer has an opening therein which at least partially exposes the lower surface of the inner semiconductor chip. A lower semiconductor chip is provided, which extends adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer. This lower re-distribution layer includes: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.