In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

At least some embodiments of the present disclosure relate to a wearable device. The wearable device comprises a substrate, a detecting module disposed on the substrate, and a control module disposed on the substrate. The control module is electrically connected to the detecting module. The control module is configured to receive a signal from the detecting module and to control the wearable device in response to the signal.

A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.

A semiconductor chip that includes a chip body that has a first side surface, a second side surface, a third side surface, and a fourth side surface; a central region at a central portion of the chip body; and a peripheral region at a peripheral portion of the chip body and adjacent to at least one of the first side surface to the fourth side surface, wherein the peripheral region includes a first unit region that includes a plurality of first bumps of a first bump density, and a second unit region that includes a plurality of second bumps of a second bump density higher than the first bump density.

Electronic modules and methods of fabrication are described. In an embodiment, an electronic module includes a molded system-in-package, and a flexible circuit mounted on a side surface of a molding compound layer such that the flexible circuit is in electrical contact with a lateral interconnect exposed along the side surface of the molding compound layer.

An electronic device includes a substrate, a first plate having a first internal surface facing a first surface of the substrate, and at least one first through-hole and at least one second through-hole, first and second semiconductor packages spaced apart from each other between the first surface and the first internal surface, a first thermal interface material layer contacting an upper surface of the first semiconductor package and the first internal surface, and filling at least a portion of the at least one first through-hole, and a second thermal interface material layer contacting an upper surface of the second semiconductor package and the first internal surface, and filling at least a portion of the at least one second through-hole. At least one of side surfaces of the first and second thermal interface material layers is exposed to an empty space between the first internal surface and the first surface.

A method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.