A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.

A semiconductor package includes a bottom package having a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die has an active surface and a rear surface coupled to the top surface of the substrate. The semiconductor die comprises through silicon vias. A top package is stacked on the bottom package. The top package comprises a memory component. A middle re-distribution layer (RDL) structure is disposed between the top package and the bottom package. The active surface of the semiconductor die is directly connected to the middle RDL structure through connecting elements. The memory component is electrically connected to the substrate via the interconnect structures of the middle RDL structure and the through silicon vias of the semiconductor die.

A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.

A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package may include a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode. The lower substrate may include a first dielectric layer, a first conductive pattern having a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern. The under-bump pattern may include a first head part and a first tail part. The first head part may have a first lateral surface on the first dielectric layer that is inclined to a top surface of the first dielectric layer. The second conductive pattern may have a second lateral surface on the second dielectric layer that is perpendicular to a top surface of the second dielectric layer.

An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. he second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.

A module includes a main board including a first surface, a submodule mounted on the first surface, a first component mounted on the first surface separately from the submodule, a first sealing resin formed so as to cover the first surface, the submodule, and the first component, and an external shield film formed so as to cover a surface and a side surface of the first sealing resin on a side far from the first surface and a side surface of the main board. The submodule includes a second component, a second sealing resin disposed so as to cover the second component, and an internal shield film formed so as to cover at least a part of a side surface of the second sealing resin. The internal shield film has at least a two-layer structure.