Patent classifications
H01L2924/10323
Enhancement-mode III-nitride devices
A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.
SEMICONDUCTOR STRUCTURE
A semiconductor structure includes heterojunction bipolar transistors arranged in parallel and disposed on a substrate. The semiconductor structure also includes a landing structure disposed at the edge of the HBTs on the substrate. The semiconductor structure also includes wiring disposed on the HBTs and connected to the landing structure. The semiconductor structure also includes an insulating layer disposed on the landing structure and having a via. The semiconductor structure also includes a bump disposed on the top surface of the insulating layer and connected to the wiring through the via. The sidewall of the landing structure has a recess in a top view.
Epitaxial structure of semiconductor device and method of manufacturing the same
Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.