A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels.

An electronics assembly comprises a semiconductor device having a first device surface and at least one device conductive layer disposed on the first device surface. A cooling structure is coupled to the semiconductor device. The cooling structure comprises a first cooling structure surface and a second cooling structure surface. The second cooling structure surface is opposite from the first cooling structure surface and the first cooling structure surface is coupled to the semiconductor device. One side cooling structure surface is transverse to the respective first and second cooling structure surface. The one side electrode is disposed on the at least one side cooling structure surface in which the at least one side electrode is electrically coupled to the at least one device conductive layer. The cooling structure includes a fluid inlet for receiving a cooling fluid and a fluid outlet for removing the cooling fluid from the cooling structure.

An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.

A transient liquid phase (TLP) composition includes a plurality of first high melting temperature (HMT) particles, a plurality of second HMT particles, and a plurality of low melting temperature (LMT) particles. Each of the plurality of first HMT particles have a core-shell structure with a core formed from a first high HMT material and a shell formed from a second HMT material that is different than the first HMT material. The plurality of second HMT particles are formed from a third HMT material that is different than the second HMT material and the plurality of LMT particles are formed from a LMT material. The LMT particles have a melting temperature less than a TLP sintering temperature of the TLP composition and the first, second, and third HMT materials have a melting point greater than the TLP sintering temperature.

A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels.

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.