An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

An integrated circuit includes a lead frame having a die attach paddle with a slot extending through the die attach paddle from a first surface to a second surface. A plurality of semiconductor die are positioned such that a channel is formed between the first, second, and third semiconductor die and the slot of the die attach paddle. A mold material encloses the plurality of semiconductor die and at least a portion of the lead frame and is disposed in the channel such that the second surface of the die attach paddle is substantially flush with the mold material. A method of forming an integrated circuit is also provided.

Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.