A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.

Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a reservoir in a surface layer on the first contact surface, the first surface layer consisting at least largely of a native oxide material, at least partial filling of the reservoir with a first educt or a first group of educts, the first contact surface making contact with the second contact surface for formation of a prebond connection, forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

There is provided a bonding material which forms a bonding portion between two objects, which material contains (1) first metal particles comprising a first metal and having a median particle diameter in the range of 20 nm to 1 m, and (2) second metal particles comprising, as a second metal, at least one alloy of Sn and at least one selected from Bi, In and Zn and having a melting point of not higher than 200 C.

A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.

A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed.