An LED device capable of emitting electromagnetic radiation ranging from about 200 nm to 365 nm, the device. The device includes a substrate member, the substrate member being selected from sapphire, silicon, quartz, gallium nitride, gallium aluminum nitride, or others. The device has an active region overlying the substrate region, the active region comprising a light emitting spatial region comprising a p-n junction and characterized by a current crowding feature of electrical current provided in the active region. The light emitting spatial region is characterized by about 1 to 10 microns. The device includes an optical structure spatially disposed separate and apart the light emitting spatial region and is configured to facilitate light extraction from the active region.

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the semiconductor die at a top surface of the conductive base, where the conductive base includes a first layer having a first coefficient of thermal expansion (CTE), and a second layer having at least one mounting tab and a second CTE. The conductive base is configured to reduce thermal stress in the ceramic case, where the first CTE is equal to or slightly different than a CTE of the ceramic case, the second CTE is greater than the first CTE, and a CTE of the PCB is greater than or equal to the second CTE. The conductive base is configured to electrically couple a power electrode of the semiconductor die to the PCB.

A semiconductor structure includes heterojunction bipolar transistors arranged in parallel and disposed on a substrate. The semiconductor structure also includes a landing structure disposed at the edge of the HBTs on the substrate. The semiconductor structure also includes wiring disposed on the HBTs and connected to the landing structure. The semiconductor structure also includes an insulating layer disposed on the landing structure and having a via. The semiconductor structure also includes a bump disposed on the top surface of the insulating layer and connected to the wiring through the via. The sidewall of the landing structure has a recess in a top view.

A semiconductor package includes a semiconductor chip formed with a semiconductor element, a heat radiating member on which the semiconductor chip is mounted via a bonding member, and a sealing member sealing the semiconductor chip. The sealing member includes a part made of a stack of a plurality of liquid crystal polymer films.

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

Semiconductor device packages are provided. In one example, the semiconductor device package includes a submount. The semiconductor device package further includes one or more semiconductor die on the submount. The one or more semiconductor die include one or more metallization layers. In one example, the one or more metallization layers include a shape-memory metallization (SMM) structure.

A semiconductor package includes a semiconductor chip, a heat radiating member on which the semiconductor chip is mounted, and a sealing member sealing the semiconductor chip. The sealing member is made of a liquid crystal polymer.