The present invention pertains to a curable organopolysiloxane composition comprising at least (A) an organopolysiloxane having at least two alkenyl groups per module, (B) an organopolysiloxane resin represented by average unit formula: (R.sup.1.sub.3SiO.sub.1/2).sub.a(R.sup.1.sub.2SiO.sub.2/2).sub.b(R.sup.2SiO.sub.3/2).sub.c(SiO.sub.4/2).sub.d. In the formula, R.sup.1's are the same or different from each other, and represent a hydrogen atom or a monovalent hydrocarbon group not having an aliphatic unsaturated carbon bond but at least two of the R.sup.1's per molecule represent hydrogen atoms, R.sup.2 represents a monovalent hydrocarbon group not having an aliphatic unsaturated bond, and a, b, and c are numbers satisfying 0<a<1, 0<b<1, and 0c0.2, and 0<d<1, respectively, but are also numbers satisfying 0.6a/d 1.5, 1.5b/d3, and a+b+c+d=1, and (C) a catalyst for hydrosilylation reaction. This composition has excellent adhesiveness to a semiconductor element, and can form a cured product in which only a small number of bubbles are produced.

A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.

A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.

An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.

An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

An optical sensor includes a substrate including a substrate main surface intersecting a thickness-wise direction, a light emitting element disposed on the substrate main surface, a light receiving element disposed on the substrate main surface, a transparent first cover disposed on the substrate main surface to cover the light emitting element, and a transparent second cover disposed on the substrate main surface to cover the light receiving element. The first cover and the second cover are spaced apart by a gap.

An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.

A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.

A distance between outermost parts of alignment chips in a direction normal to a surface of a substrate is different between a first direction and a second direction along terminal placement surfaces. The plurality of alignment chips include a first alignment chip fixed to a first metal pad, and a second alignment chip fixed to a second metal pad. The first alignment chip and the second alignment chip are oriented in different directions on the surface of the substrate. A semiconductor module includes a first side surface part extending in the second direction and facing the first alignment chip, and a groove part formed in a portion of the first side surface part. A portion of the second alignment chip is positioned in the groove part.